1. Field
The present disclosure generally relates to the design of a chip package. More specifically, the present disclosure relates to the design of a chip package that facilitates batch-processed, three-dimensional integration.
2. Related Art
As integrated-circuit (IC) technology continues to scale to smaller critical dimensions, it is increasingly difficult for existing inter-chip connections to provide suitable communication characteristics, such as: high bandwidth, low power, reliability and low cost. For example, as the operating frequencies continue to increase, it is difficult to maintain the performance of interconnects between conventional individually packaged chips that are connected to a printed circuit board. As a consequence, engineers are researching alternative chip-packaging technologies.
One chip-packaging technology that has been proposed to address this problem is a multi-chip module (MCM) in which mechanically and electrically coupled chips are arranged in a three-dimensional (3D) structure. For example, chips in different layers in the 3D structure may be electrically coupled using dense inter-chip connections, with a pitch between neighboring pads on the order of 10-100 μm.
However, the dense interconnects and the multiple components in the MCM can pose additional packaging challenges. In particular, in order to achieve high-bandwidth/high-data-rate inter-chip communication, the mechanical alignment between facing chips in the MCM typically needs to be on the same order as the pitch between neighboring pads. It can be challenging to position the chips in the MCM with the required accuracy at high speed, which can adversely impact the cost or the performance of the MCM.
Hence, what is needed is a chip package that does not suffer from the above-described problems.